On August 18, 2008, Cadence Design Systems released the SPB version 16.2 to address current and emerging chip package design issues. This latest release provides advanced IC package/system-in-package (SiP) miniaturization, design cycle reduction and DFM drive design, as well as a new power integrity modeling solution. These new features increase the efficiency of digital, analog, RF, and mixed-signal IC package designers working in single- and multi-chip packages/SiPs.
The design team will see the introduction of new rules and constraint-oriented automation capabilities that address the design methodology of high-density interconnect (HDI) substrate fabrication, which is important for miniaturization and increased functional density. The stimuli, so that the overall package size is greatly reduced by facilitating team-based design, multiple designers can simultaneously design the same design, which can shorten the design cycle, greatly shorten the total design time, and achieve a fast time to market.
Today's industry is focused on low-power design, especially in wireless devices and battery-operated devices. Efficient power supply networks (PDNs) are critical to meeting power management goals. The new power integrity technology allows designers to efficiently solve power supply design problems and achieve sufficiency, efficiency and stability in power usage.
"The sophisticated high-speed ICs at the cutting edge create very challenging IC package designs, including physical implementation and signal and power integrity," said Kevein Ross El le, CTO of BaysideDesign. "With the current miniaturization and design enhancements With the efficiency of the division and the focus on efficient PDN design, we feel that SPB 16.2 will help designers better solve their design challenges."
In addition, through an agreement with manufacturing equipment leader Kulicke & Soffa, Cadence used the Kulicke & Soffa-certified bond wire IP configuration library to achieve DFM-oriented bond wire design, increased yield and reduced manufacturing delays.
"As bond wire packaging becomes more complex, designers are facing the challenge of DFM matching within the design to avoid manufacturing problems," said Paul Reid, product marketing manager at Kulicke & Soffa. "Through cooperation, we can now Designers provide a library for DFM bond wire configuration."
"This new version provides important improvements for our IC packaging and SiP technology, and we are pleased to see that companies such as BaysideDesign have benefited from it," said Steve Kamin, Head of Product Marketing at Cadence. "We are committed to improving our technology, with Leading vendors in the design chain connect to maintain our leadership in helping designers achieve or even exceed their design goals."
SPB 16.2 will be available in the fourth quarter of 2008. Customers can see samples of AllegroPCB and IC package/SiP processes at the CDNLive! Silicon Valley conference from September 9th to 11th, or register as a techtorial member on September 8. At the same time, the SPB 16.2 version will be on display at the EMA booth at the PCBWest show in Santa Clara from September 14th to 19th.
The design team will see the introduction of new rules and constraint-oriented automation capabilities that address the design methodology of high-density interconnect (HDI) substrate fabrication, which is important for miniaturization and increased functional density. The stimuli, so that the overall package size is greatly reduced by facilitating team-based design, multiple designers can simultaneously design the same design, which can shorten the design cycle, greatly shorten the total design time, and achieve a fast time to market.
Today's industry is focused on low-power design, especially in wireless devices and battery-operated devices. Efficient power supply networks (PDNs) are critical to meeting power management goals. The new power integrity technology allows designers to efficiently solve power supply design problems and achieve sufficiency, efficiency and stability in power usage.
"The sophisticated high-speed ICs at the cutting edge create very challenging IC package designs, including physical implementation and signal and power integrity," said Kevein Ross El le, CTO of BaysideDesign. "With the current miniaturization and design enhancements With the efficiency of the division and the focus on efficient PDN design, we feel that SPB 16.2 will help designers better solve their design challenges."
In addition, through an agreement with manufacturing equipment leader Kulicke & Soffa, Cadence used the Kulicke & Soffa-certified bond wire IP configuration library to achieve DFM-oriented bond wire design, increased yield and reduced manufacturing delays.
"As bond wire packaging becomes more complex, designers are facing the challenge of DFM matching within the design to avoid manufacturing problems," said Paul Reid, product marketing manager at Kulicke & Soffa. "Through cooperation, we can now Designers provide a library for DFM bond wire configuration."
"This new version provides important improvements for our IC packaging and SiP technology, and we are pleased to see that companies such as BaysideDesign have benefited from it," said Steve Kamin, Head of Product Marketing at Cadence. "We are committed to improving our technology, with Leading vendors in the design chain connect to maintain our leadership in helping designers achieve or even exceed their design goals."
SPB 16.2 will be available in the fourth quarter of 2008. Customers can see samples of AllegroPCB and IC package/SiP processes at the CDNLive! Silicon Valley conference from September 9th to 11th, or register as a techtorial member on September 8. At the same time, the SPB 16.2 version will be on display at the EMA booth at the PCBWest show in Santa Clara from September 14th to 19th.
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