High-performance floating-point processing has traditionally been the domain of high-end CPUs. However, in recent years, GPUs have emerged as powerful platforms for floating-point computations, expanding beyond their original role in graphics to become general-purpose GPU (GPGPU) devices. A newer innovation is the use of FPGAs for floating-point processing in demanding applications. This article focuses on the capabilities of FPGAs in terms of floating-point performance and design flow, along with the use of OpenCL, a programming language that enables high-performance computing at the frontier of floating-point operations.
The GFLOP/s metric across various platforms continues to evolve, and now TFLOP/s is commonly used. However, peak GFLOP/s values often provide limited insight into actual device performance, as they represent theoretical maximums rather than real-world results. Analysis shows that FPGA-based single-precision floating-point processing can exceed 1 TFLOP/s, making it a compelling choice for certain applications.
A less common but widely used algorithm is the Fast Fourier Transform (FFT). Implementing a 4096-point FFT using single-precision floating-point allows four complex samples to be processed per clock cycle. Each FFT core runs faster than 80 GFLOP/s, and a large FPGA can support up to seven such cores. As shown in Figure 1, the overall FFT performance of this FPGA reaches nearly 400 GFLOP/s through a "button-on" OpenCL compilation that requires no deep FPGA expertise. With optimizations like logic lock and design space exploration (DSE), the 7-core design achieves performance close to that of a single-core design, raising its GFLOP/s to 500 while maintaining an efficiency of over 10 GFLOP/s per watt.
This level of efficiency far surpasses that of CPUs or GPUs. In contrast, GPUs are not particularly efficient for these FFT lengths, so benchmarks were not conducted. However, when the FFT length increases to hundreds of thousands of points, GPUs become more efficient, offering effective acceleration for CPU-based systems.
In summary, actual GFLOP/s typically only reach a fraction of the theoretical peak. Therefore, comparing performance based on algorithms provides a more accurate representation of real-world application characteristics. The more complex the algorithm, the more representative the benchmark. Instead of relying solely on vendor-reported peak GFLOP/s metrics, third-party assessments offer a more sophisticated and realistic evaluation.
The Cholesky decomposition is an ideal algorithm for high-performance computing. It is widely used in linear algebra for solving multiple equations and matrix inversion. Due to its complexity, it requires floating-point representation to achieve meaningful results. Its computational demand scales with N³, where N is the matrix dimension, making it highly resource-intensive. Actual GFLOP/s depends on the matrix size and required throughput.
Table 1 presents benchmark results for the Nvidia GPU (1.35 TFLOP/s) and the Xilinx Virtex6 XC6VSX475T, optimized for DSP processing. These devices are comparable in density to Altera FPGAs when tested with Cholesky decompositions.
LAPACK and MAGMA are commercial libraries, while the GPU GFLOP/s implementation uses OpenCL developed by the University of Tennessee. For smaller matrices, the latter is more optimized. The mid-range Altera Stratix V FPGA (460kLE) was also benchmarked using the single-precision Cholesky algorithm. As shown in Table 2, the performance of the Cholesky algorithm on Stratix V FPGAs significantly outperforms Xilinx results.
It’s important to note that the matrix sizes differ between benchmarks. The University of Tennessee started with a [512 x 512] matrix, while BDTI reached a [360 x 360] matrix. GPUs are inefficient for small matrices, so they are not suitable for accelerating the CPU in such cases. FPGAs, on the other hand, perform efficiently even with smaller matrices.
The BDTI benchmark includes a Cholesky kernel that allows selection of matrix size, vector size, and number of channels. Larger matrices require longer vectors to support the core, achieving 91 GFLOP/s. Smaller matrices use fewer resources, allowing multiple cores to run in parallel, increasing total performance. For example, a [60 x 60] matrix supports two cores, totaling 78 GFLOP/s, while a [30 x 30] matrix supports three cores, totaling 78 GFLOP/s as well.
FPGAs appear better suited for smaller data sizes due to the cubic increase in computational load versus the quadratic increase in data I/O. As data grows, the GPU’s I/O bottleneck becomes less of an issue. Throughput also decreases with larger matrices, leading many applications to decompose large matrices into smaller sub-matrices.
For FFT, the computational load increases with N logâ‚‚N, while I/O increases linearly with N. Thus, GPUs are more efficient for large FFTs, while FPGAs excel for shorter FFTs, typically in the range of thousands of points. GPUs are more efficient for FFTs in the hundreds of thousands of points.
GPU and FPGA Design Methods
GPUs are programmed using CUDA or OpenCL. While similar in functionality, CUDA is exclusive to Nvidia GPUs. FPGAs are usually programmed in HDL languages like Verilog or VHDL. Though these languages support floating-point definitions, they are not well-suited for floating-point designs. For example, System Verilog uses 'short real' for IEEE single precision and 'real' for double precision.
Integrating floating-point datapaths into FPGAs using traditional methods is inefficient. Xilinx FPGAs show low performance on the Cholesky algorithm unless using their floating-point kernel generation feature. Altera offers two approaches: one involves Mathworks-based design input, called the DSP Builder Advanced Module Library, which supports fixed and floating point numbers, including 7 different precisions. It also supports vectorization for efficient linear algebra implementation and maps floating-point circuits to fixed-point architectures effectively.
OpenCL compilation for FPGAs allows code written for AMD or Nvidia GPUs to be compiled for FPGAs, eliminating the need for traditional FPGA development. OpenCL offers several advantages over GPUs, including wider I/O capabilities and lower latency. FPGAs support data transfer via Gigabit Ethernet or directly from ADC/DAC inputs, while GPUs rely on PCI interfaces, causing delays.
FPGAs use a coarse-grained parallel architecture, establishing multiple optimized parallel data paths that produce one result per clock cycle. This architecture leads to lower latency, which is critical in many applications. Additionally, FPGAs consume much less power, resulting in higher GFLOP/s per watt. For instance, the Cholesky algorithm on FPGAs achieves 5–6 GFLOP/s per watt, compared to just 0.25 GFLOP/s per watt for GPUs.
Both OpenCL and DSP Builder rely on fused data path technology, enabling efficient floating-point processing on FPGAs. This reduces barrel shift circuits, supporting large-scale, high-performance floating-point designs. By maximizing mantissa width during synthesis, normalization and denormalization steps are minimized, improving performance.
In vector multiplication, a single-precision implementation of a 64-length vector requires 64 multipliers and 63 adders. Traditional methods involve extensive barrel shifting. However, by denormalizing outputs and summing them with fixed-point adders, the need for temporary normalization is eliminated, reducing complexity.
This method produces more accurate results than traditional IEEE754 floating-point calculations. As shown in Table 3, BDTI benchmarks confirm the accuracy of this approach. Using the Cholesky decomposition algorithm, the results demonstrate that the fused data path method is significantly more accurate than single-precision implementations, with a precision improvement of up to 10â¹ times.
These advancements highlight the growing importance of FPGAs in high-performance computing. With innovations in architecture and process technology, FPGAs can now deliver up to 100 peak GFLOPs/W. Tools like Altera’s OpenCL compiler and DSP Builder Advanced Blockset further streamline development, providing GPU programmers with seamless access to FPGA-based computing.
In conclusion, FPGAs offer low latency, high GFLOP/s, and excellent energy efficiency, making them a compelling choice for high-performance computing. As next-generation FPGAs continue to evolve, their advantages will become even more pronounced. Whether for GPU developers or non-GPU specialists, FPGAs are proving to be a versatile and powerful platform for modern computing needs.
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