IC Design Industry: Reshaping the New Value Chain

December 17 news, 2012 will be turning pages, each industry ups and downs or cold and warm know. This year, China's IC design industry passed the "risk of danger" and became "the most difficult but continuous progress" in its history. At the recently held 2012 China IC Design Industry Annual Conference and Chongqing IC Innovation and Development Summit Forum, Wei Shaojun, Chairman of IC Design Branch of China Semiconductor Industry Association pointed out that China's IC design industry has achieved good results in this year. This is reflected in the continued growth in the scale of the industry, the continued improvement in the quality of development, the increase in competitiveness, and the significant improvement in corporate profits. In 2012, IC design industry sales will reach 68.045 billion yuan, an increase of 8.98% year-on-year. The position of the IC design industry in the Chinese mainland has been further consolidated in the global industry, continuing to remain third in the United States and Taiwan.

Depth breadth parallelism

Communications, smart cards, computing, multimedia, analog, power, navigation, and consumer products are the top ten markets for IC design in mainland China. Because the design industry in China has its own characteristics, it needs to combine the three-dimensional strategy of upstream and downstream companies to meet the diversified needs.

In terms of process selection, Wang Guoyi, deputy general manager of Asia Sales and Marketing Department of UMC, did not agree with the industry's pursuit of advanced manufacturing processes. He pointed out that currently no more than 20% of semiconductor manufacturers adopt 28nm process technology, and 80% of customers still remain in the mature process stage. Luo Zhenqiu, deputy general manager of TSMC China Business Development, also told the China Electronics News reporter that the needs of the IC market in mainland China are to provide relatively complete functions and customers can afford it. If advanced processors are used to develop processors, U.S. companies can design their main frequency to reach 2G, China's Taiwan region can reach 1.7G, and mainland China can only achieve 1.5G, but consumers feel similar when applied. Therefore, IC companies in mainland China will use appropriate processes to form suitable products and will grow rapidly.

With IC design entering the SoC era, more than 90% require IP authorization, or integrated design through its own IP.

Pan Jianyue, Global Vice President and President of Asia-Pacific, Synopsys, believes that the IC industry in Mainland China is catching up with advanced international standards, while the IC industry in foreign countries has developed for many years and has accumulated endogenous IP. IC industry in mainland China needs to achieve leapfrog development. Need mature IP. In addition, the IC industry in mainland China is expanding both in depth and breadth. In terms of depth, IC design in Mainland China has advanced processes such as 32nm, 28nm, or even 22nm; in terms of breadth, the distribution of process coverage is very wide. Requires EDA tool vendors have the ability to provide targeted tool services and IP.

The homogeneity competition of the IC design industry in mainland China is severe, and the problem of being referred to as an IP processing plant has also been criticized. However, Cadence president and CEO Chen Liwu pointed out that although the IP cores adopted by IC companies in mainland China are not much different, they are not in the same structure. Aspects, such as the connection between the core and the core, the connection with the memory, the clock is 4 or 8 phase, how to use the EDA tool to improve the development efficiency and success rate, how to use the EDA tools, and the success rate can be differentiated. It is not the same IP. The same process cannot be differentiated.

The mainland China IC industry currently has more than 500 companies, each at a different development node. Wang Guoxi said that they will go through three stages of development: First, to seize the market, after occupying a place, enter the second stage that is to make money stage, the third is the sustainable development stage. At present, most of the IC design companies in mainland China are in the first stage, and some have entered the stage of making money. The performance of making money is listed and the second is acquisition. It is still very difficult to really reach the third stage because it requires a globalized layout, patent layout, and product depth.

Reshaping the value chain

With the increasingly complex design of embedded processor and mixed-signal SoC products in the semiconductor industry and the emergence of advanced manufacturing processes represented by FinFETs and 3D ICs, it is necessary to consider a series of complicated conditions involving speed, power consumption, and cost during development. Personnel must use all their tools, including new circuit designs, new architecture methods, and radically modify the algorithms so that they can continue to achieve better performance at a competitive price, while power consumption is within an acceptable range. Internally, this involves algorithm design, software development, circuit board design, and ultimately package and thermal design. This has brought new challenges to EDA suppliers, IP suppliers, and foundries in the IC design industry chain. The challenge to IC design upstream and downstream also means the reshaping of the industrial value chain.

EDA tools need to provide systematic simulation and verification schemes, software and hardware co-acceleration simulation and verification schemes, and EDA suppliers increase their R&D investment in advanced 3D IC technology, low-power design, and large-scale collaborative verification. And mergers and acquisitions. Synopsys recently completed the acquisitions of two companies. First, it spent $200 million to acquire EVE, a provider of SoC verification simulation acceleration platforms, thereby adding a high-performance, high-capacity simulation acceleration capability to its verification platform. The second is to spend 400 million US dollars to acquire SpringSoft, which will enhance its ability to correct errors in the verification process. Li Runhua, technical director of Asia Pacific at Mentor (Shanghai) Electronic Technology Co., Ltd., said that as the chips become more and more complex, the verification cycle becomes longer and longer. In addition to software simulation and FPGA simulation, hardware simulation acceleration will become the mainstream in the future. Significantly reduce verification time and improve verification efficiency. Chen Liwu said that Cadence is also committed to vertical integration and cooperation with ARM, TSMC, ARM companies consider how to use the potential of EDA tools, Cadence consider tool efficiency and optimization, one-on-one personal service. In June of this year, Cadence cooperated with TSMC to produce the first 3D IC experimental chip. In October, Cadence worked with IBM to design and implement the first ARM Cortex-M0 processor based on the IBM 14nm and using IBM's FinFET process technology.

Wang Yanwei, Marketing Manager of Beijing Huada Jiutian Software Co., Ltd. also mentioned that in a 20nm process, a mobile application chip contains more than 1 billion transistors, EDA tools face more complex verification and DFM challenges, and need to support double Patterning (double graphics) and other new technologies. With the application of new technologies such as FinFETs and 3D ICs, EDA needs to study the mechanism of devices and the precision and standardization of complex models. The effects of electromigration will also be the key problems that EDA tools must tackle.

The design service companies that play "intermediaries" of design companies and EDA tools, IP suppliers, and foundries in the industrial chain are also changing on demand. Gu Jianyu, president of Wuxi Huada Guoqi Technology Co., Ltd., said that the role of design service companies is evolving: in cooperation with IC design companies, they must participate in SPEC formulation, provide low-power strategy and algorithm support, etc. IP development capabilities, reasonable IP accumulation, IP resource integration, etc.; in EDA tool applications, design flow management, locally owned EDA tools, various scripts, etc.; in the process, have a deep understanding of advanced processes .

Dai Weimin, chairman and president of VeriSilicon Microelectronics (Shanghai) Co., Ltd., also stated that from the perspective of the IC industry, the Fab-lite and Design-Lite models in Mainland China are prevailing; the second is that the previous suitable IP is not very good, now Companies such as the ARM core and Synopsys can provide a lot of IP libraries to choose from, which makes the design more convenient. Third, as chips become more and more of a SoC, software becomes more important, and the design vendors need to focus on architecture and software.

The post-Moore era triggered ecological change

Wei Shaojun said that when technological progress no longer follows the law of doubling the degree of integration every two years, the development road map and technology route of the industry are no longer quite certain, and when the basic basic device structure and manufacturing process have undergone fundamental changes , entered the so-called "post-Moore" era, based on this consideration, starting from 22nm/20nm we will enter the "post-Moore" era.

With the arrival of the post-Moore era, great changes will take place in both IC technology and industrial ecology. Wei Shaojun pointed out that first, the business model will fundamentally change. Since the value of IC depends on the application of electronics and systems, it will be difficult to ensure that the value of IC products is maintained at a relatively high level. The second is that software is indispensable. The content of the architecture design will include chip and chip software, and the software will evolve from passively following chip upgrades to product definition that actively guides the chip; thirdly, EDA vendors will become partners. High R&D costs will require EDA vendors to provide more customized services to design companies, and one-on-one “self-service” will become a challenge that EDA vendors have to face.

Faced with the new "era", IC design companies need to be prepared for everything. Wei Shaojun stated that problems such as floating process and yield will become increasingly prominent. New devices such as FinFET will lead to fundamental changes in chip R&D. Design companies must not only understand the design, but also must fully enhance their physical design capabilities. They must also understand the process and even must build strong. Powerful craft team etc. At the same time, we must target large-scale mainstream products in products, and should be bigger and stronger in the industry as soon as possible. In the 20nm node, because a chip product needs sales of 60 million to 100 million to achieve the balance of profit and loss, only general platform products will be accepted, this will not be an ASIC, only a large number of ASSP, such as Mobile communication terminal chip or digital television chip.

In addition, Luo Zhenqiu said that in the process of choice, because the 28nm process uses HKMG technology, 16nm is using FinFET technology, to the 10nm node, perhaps each will have a different game. This also requires more close cooperation between IC design vendors and foundries. Chen Liwu said that with the advancement of advanced technology, new requirements have been put forward for EDA tools. For example, from 28nm to 20nm, EDA has changed a lot because of the need to light twice. In addition, FinFET chips have different EDA physical verification tools. Claim. With the arrival of the advanced technology 20nm era, Cadence will continue to promote the "simulation design constraints" new method to reduce design errors under the premise of ADE; continue to strengthen the function of PDK to improve design efficiency.