Application of dual-port RAM in ARM and DSP communication system [Figure]

In the post-PC era, due to the rapid development of network technology and integrated circuit technology, it has become possible to use embedded systems for digital signal processing and transmission. In the dual-processor system composed of ARM and DSP, embedded as the master device mainly completes data processing, storage and network transmission work, while DSP as the slave device needs to be responsible for the implementation of complex algorithms.

In this high-speed data acquisition and processing system, with the increase in the amount of sampled data and the increase in processing tasks, the requirements for data transmission are getting higher and higher. If there is no interface between the two system ports that can transmit data at high speed, It will cause blockage of data transmission and seriously affect the real-time performance of the system and the ability to process data. Therefore, one of the focuses of this system design is the data communication between the master and slave devices. This article introduces the use of dual-port RAMIDT70261 to complete the data communication between TMS320C6211DSP and embedded ARM920T.

1 IDT70261 dual port RAM function introduction

IDT70261 is a high-speed 16K & TImes; 16 dual-port SRAM produced by American IDT Company. Its typical power consumption is 750mW, and it has two levels of access time: commercial grade has 15/20/25/35/55 ns (max), Industrial grade has 20/25/35 / 55ns (max). The dual-port RAM has two completely independent ports, each of which has a corresponding set of data bus, address bus, and control bus, allowing the two controllers to read or write any one of the storage units individually or asynchronously. The two ports have the same ability to read and write to the dual-port RAM, but when the two ports read and write to the same address at the same time, it will cause storage or read errors due to data conflicts. There are four cases for the operation of the same storage unit:

(1) The two ports do not read or write data to the same address unit at the same time.

(2) The two ports simultaneously read data from the same address unit.

(3) Two ports write data to the same address unit at the same time.

(4) Two ports simultaneously write data to one address unit, one reads data from the other.

The first two cases will not cause a read or write error to the dual-port RAM, the third case will cause an error in writing data, and the fourth case will cause a readout error. In order to avoid reading and writing errors to the dual-port RAM, IDT70261 has the following arbitration control methods.

1.1 Busy logic control

When dual ports control the same address unit at the same time, IDT70261 provides a / BUSY control mechanism. When the two ports do not control the same address unit, the / BUSY pin of both ports is high, and the left and right ports can normally access the storage space. When two ports access the same address unit, the / BUSY pin of one port is high (allows read and write operations to the storage space), and the pin of the other port is low (prohibits read and write operations to the storage space ), Whichever request signal comes first, its port pin is high and the other is low. The minimum time difference between the two ports to request read and write is 5ns. When the time is less than 5ns, the system will automatically allow one pin to read and write, shield the other pin, and prevent the read and write errors of the same address unit.

1.2 Interrupt control mechanism

IDT70261 has an interrupt output function. When interrupting work, the two highest address units 3FFE and 3FFF of the dual-port RAM are used as "mailboxes" to transfer the corresponding commands. When the interrupt function is not used, the two units 3FFE and 3FFF are used as normal storage units. The following describes the interrupt working principle.

The left port writes the address unit 3FFF, / INTR becomes active (low level), sends an interrupt request to the right port, after the right port responds to the interrupt request, it can perform a read operation to the 3FFF address unit to clear the interrupt flag (/ INTR becomes High level). Similarly, the right port writes the address unit 3FFE, / INTL becomes active (low level), sends an interrupt request to the left port, and after the left port responds to the interrupt request, it can perform a read operation to the 3FFE address unit to clear the interrupt flag (/ INTL goes high).

1.3 Principle of token passing

IDT70261 has 8 logic latch units independent of dual-port RAM to indicate whether the shared dual-port RAM is in use. In this working mode, / SEM is used as the "chip select" signal of the latch, address lines A2 ~ A0 are used to address the 8 flag latches, and data line D0 is used to flag the latch status.

The port writes 0 to the latch to apply for control, and writes 1 to give up the right to use. When the left port wants to use dual-port RAM, first write 0 to the flag latch, and then read the status of the flag latch. If the value read is 0, the left port obtains the right to use the storage unit; The read value is 1, indicating that the right port is using the storage unit.

At this time, the left port will either cyclically detect the latch status until the right port is used up, or write a 1 to the latch to cancel the request. Similarly, if the right port uses dual-port RAM, follow the above steps [1,2].

2 Interface circuit based on IDT70261

This system is a video data acquisition and processing system. When the data collected by the camera is compressed and encoded by the DSP and input into the dual-port RAM chip, the ARM processor receives the image request, receives the image data, and stores and transmits the data. Decode the image and display it on the terminal PC.

The interface circuit diagram based on IDT70261 is shown in Figure 1. This system uses an interrupt control mechanism, and some function pins of the dual-port RAM do not need to be fully used. The left end of the dual-port RAM is the ARM920T chip, and the right end is the TMS320C6211 DSP chip. The two independent data lines D0L-D15L and D0R-D15R of the dual-port RAM are respectively connected to the ARM920 chip and the DSP chip, and the address lines A0L-A13L and A0R-A13R are also respectively connected to the above two chips. / CE is the chip enable pin, R / W is the read and write control pin, / OE is the output enable pin, / INT is the interrupt flag pin, / BUSY is the busy control pin, and the connection circuit is as shown in the figure 1 shown.

Figure 1 Interface circuit

3 Software implementation of data communication

This system adopts the interrupt control mode to realize the read and write operations to the dual-port RAM. The DSP is mainly responsible for image data compression. The compressed data is transferred to the dual-port RAM. When transferring data, the DSP writes '55H' to the signaling word unit 3FFF. After the ARM generates an interrupt, the ARM reads the signaling word unit 3FFF. If it is '55H', it means the data is being transmitted. After reading the data, write 'AAH' to the signaling word unit 3FFE, which means reading the data. After the DSP receives the interrupt, it reads the signaling word unit 3FFEH. If it is 'AAH', it indicates that the data transmission was successful.

ARM completes the real-time control of the entire system, reads the image data of the dual-port RAM and transmits it to the PC through the network. Therefore, a driver is required to realize the data communication between the dual-port RAM and ARM. The driver is the interface between the application and the hardware, and the user can indirectly realize the read-write control operation of the hardware through the driver. The main task of the dual-port RAM driver is to read the dual-port RAM data to user space, write user space commands to the corresponding address of the dual-port RAM, and the interrupt generated by the corresponding dual-port RAM. In the driver, the most important structure is file_operaTIon, which contains the file opening, closing, reading and writing, and other control functions. The structure of file_operaTIon is as follows:

Before using the device, you need to initialize the device, including configuring the ARM interface registers, registering the device, applying for interrupts, and allocating virtual address space. The configuration register and registration application are implemented when the module is loaded, and the resource allocation is implemented in the dualram_open function.

Configure the interface register. AT91RM9200 has an EBI interface, which can be easily connected to various storage devices. You can use the SMC in the EBI interface to control reading and writing. The CS4 interface controls the enable signal of the dual-port RAM by writing to the corresponding register. Enter the control word to realize the initialization of the dual-port RAM by ARM.

In the initialization function init_dualram, use register_chrdev to register the dual-port RAM as a character device, and use request_irq to apply for the corresponding interrupt resource for the device. The functions are as follows:

myirq = request_irq (AT91RM_IRQ1, dualport_inter, SA_INTERRUPT, "dualram", NULL)

Register and apply when loading the driver, and unregister when unloading the module, that is, execute unregister_chrdev and free_irq in dualram_exit to release resources.

Linux cannot directly access a physical address space, and must complete the access through the mapping mechanism of the virtual address space. The mapping work is done in the dualram_open function, so it will be done every time the device is opened. The address resources and data structures to be used are defined as follows:

#define dualram_base_addr 0x60000000

#define dualram_size ox3fff

u16 * remaddr

By using the function remaddr = ioremap (dualram_base_addr, dualram_size); for virtual address mapping, you can then use remaddr to complete access to the actual dual-port RAM space.

In order to effectively improve the data transmission efficiency, an asynchronous notification mechanism is used between the driver and the application, so that the upper-layer application can know whether the amount of data in the RAM reaches the threshold, instead of polling, which consumes processor resources. The asynchronous notification mechanism is completed in three steps. First, you need to let the kernel know which process the driver communicates with. When the process uses the system function fcntl to execute the F_SETOWN command, the ID number of the device file owner (owner) will be recorded in flip-》 f_owner At this time, the kernel knows the process of communicating with the driver, and then the application calls fcntl's F_SETFL command to activate the asynchronous notification mechanism, so that when new data arrives, the input file can send a SIGIO signal to the process specified in flip-》 f_owner.

After the image data arrives, the application in Linux completes the read and write operations on the data. The write operation function is: dualram_write, which uses copy_from_user to write user space data to the dual-port RAM. The read operation function: dualram_read, which uses copy_to_user Read the data in the dual-port RAM into the user space [5, 7].

4 Test results

The test environment of the video monitoring system is that ARM 920T and TMS320C6211 are interconnected with PC through the network to form a simple local area network. Through the network packet capture software, the data traffic of the network can be counted, and the real-time nature of the system can be analyzed through the CCS analysis tool. The higher the quantization step of the system, the greater the compression ratio of the image, and the worse the quality of the obtained image. The quantization step set by this system is set to 75. The main parameters of this system after testing are as follows: the compression format of the image is JPEG, The resolution is BMP (240 & TImes; 160), the maximum encoding speed is 15 frames / second, the data flow is 50-200kbps, the network uses UDP / IP protocol, and the network interface is RJ-45 100Mbps.

5 Conclusion

This article combines the design of the embedded image data acquisition system and introduces the communication between the ARM920T and the TMS320C6211 DSP through the dual-port RAM. Using the powerful functions of dual-port RAM can achieve high-speed data communication between various forms of processors. In the field of signal processing and high-speed data collection, the use of several different arbitration mechanisms of dual-port RAM can complete different data transfer requirements.

The interface circuit formed by it has the advantages of high transmission rate, good real-time performance, high reliability and simple circuit.

Scope of supply

Rating: Up to 200MVA

Voltage:Valve side voltage up to 1000VDC, Grid side voltage up to 220KV

Double star and double bridge



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Electrolysis is normally a continuous process, but with a constant high loading and current harmonics.



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