Decryption: Why are digital circuits more efficient than low levels?

In fact, it is determined by the common circuit structure. When the circuit is low, the circuit tends to have a lower loop impedance at a higher level, while the lower impedance means more anti-interference capability. Combine practical examples with a practical example to deepen your impression:

Some of our classmates may have learned such a PCB layout rule----in the case of conditional permission, the active-high line should be shortened as much as possible, and the active-low line should be extended as much as possible----this one The basis of the existence of the rule is that the loop impedance is relatively low based on the low level, and the anti-interference ability is relatively strong.

For example, the OC or OD circuit needs to control a level through the on and off of this switch. In the case of a pull-up resistor, the switch is turned on, and it is low; the switch is turned off, and it is high. In this way, in order to prevent the circuit from being out of control, it is still an effective level, then of course it is more effective to be "insecure". Structurally, like the OC circuit, since the collector is more difficult to break down, it is less likely to be damaged.

For other totem pole output circuits, although 0 and 1 have the same risk, there are still people in the application who are willing to add a pull-up resistor to achieve OC or OD output. As for why you don't use pull-down resistors and pull-up resistors, you can analyze them.

Another aspect is the OC or OD output circuit, which uses an energy-saving effect after using a pull-up resistor. Because it is turned off, it has almost zero current when it gets high.

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